PCBA DFM Checklist

📋 Schematic & BOM

Component selection

• All critical components (long lead, near-obsolete) checked for 10k+ stock at 3+ distributors
• BOM format is CSV with MPN, manufacturer, quantity, reference designator, description
• Footprints generated from datasheet, not generic library (verified with IPC-7351)
• Decoupling caps within 2mm of every power pin
• Crystal within 5mm of IC, with proper load cap placement
• Test points on every power rail (3.3V, 1.8V, VBAT, GND)
• Accessible ground vias on every power domain

Schematic review

• Power-on reset timing verified (POR supervisor if MCU has none)
• Strapping pins have explicit pull-up/pull-down (no floating)
• Unused IC pins handled per datasheet (no floating inputs)
• ESD protection on external connectors (USB, antenna, buttons)
• Reverse polarity protection on power input (Schottky or P-FET)
• Battery protection IC for Li-Ion/Li-Po cells
• Programming/debug header accessible (SWD, JTAG, UART)

🔌 Layout & Stackup

Stackup

• 2-layer for simple designs (low-cost, slow signals)
• 4-layer for typical designs with digital + power (recommended)
• 6-layer for high-speed signals (USB 3.0, HDMI, MIPI)
• 8-layer for RF + high-speed digital mixed (WiFi, BLE + MCU)
• Power plane adjacent to ground plane (decoupling)
• Controlled impedance traces calculated and verified (50Ω single-end, 90Ω diff)

DFM rules

• Minimum trace width: 0.1mm (4 mil) for signal, 0.2mm (8 mil) for power
• Minimum trace spacing: 0.1mm (4 mil) for low voltage, 0.2mm for >12V
• Minimum drill: 0.3mm (12 mil) mechanical, 0.25mm (10 mil) via
• Minimum annular ring: 0.13mm (5 mil)
• Copper-to-edge: 0.3mm minimum (avoids exposure during fab)
• 3 fiducials on every panel (1 panel-level, 2 board-level)
• Thermal relief spokes on pads connected to large copper pours
• Silkscreen 0.2mm clearance from exposed pads

🛠️ SMT Assembly

Component placement

• Tallest components on top side (avoid 2-side reflow issues for prototypes)
• Polarized components all in same orientation (easier inspection)
• BGA with keep-out for via-in-pad (or use proper via-in-pad plating)
• Fine-pitch components (≤0.5mm) away from board edge
• 0.5mm clearance between components for rework
• Heatsink mounting area clear of tall components

Solder mask & paste

• Solder mask defined pads (NSMD recommended for fine-pitch)
• Mask slivers less than 0.1mm removed (DFM catch)
• Via tenting on signal layers (avoid solder wicking)
• Stencil apertures reduced for QFN/BGA thermal pads (70-80% coverage)
• Step-up stencil for mixed component heights

🧪 Test & Quality

Design for testability

• ICT test points: 0.5mm pads on 1.27mm pitch grid
• Power rails accessible for voltage measurement
• Boot mode pin accessible from outside (for programming/recovery)
• LED indicators for power, status, fault
• JTAG/SWD accessible for boundary scan
• Self-test firmware included (validates key functionality at boot)

Compliance pre-check

• FCC: intentional radiator (Bluetooth/WiFi) needs FCC ID testing
• CE: EN 301 489 (EMC), EN 300 328 (2.4 GHz), EN 62368-1 (safety)
• Apple MFi: required for any Lightning/Find My product
• Google Find Hub: GMS certification for Android compatibility
• UL: required for products with AC input or Li-Ion batteries
• RoHS: lead-free HASL or ENIG finish, no lead-based components
• REACH: SVHC declaration for EU market
• UN38.3: required for any product shipping with Li-Ion/Li-Po batteries

📋 Documentation deliverables

• Gerber files (RS-274X format) for all copper layers
• Drill files (Excellon format)
• Pick-and-place files (CSV with X, Y, rotation, side)
• BOM (CSV with MPN, manufacturer, qty, refdes, description)
• Schematic (PDF + native format)
• 3D model (STEP file) for enclosure fit check
• Assembly drawing (PDF)
• Test procedure (for EMS to follow)